1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device including an assist gate.
2. Description of the Background Art
Various attempts have conventionally been made in order to reduce a size of a non-volatile semiconductor memory device (see Japanese Patent Laying-Open No. 2000-188346). An AG-AND type flash memory has been proposed as a technique to make smaller a non-volatile semiconductor memory device. In the AG-AND type flash memory, a bit line of a memory cell transistor is implemented not by a diffusion layer but by an inversion layer formed on a main surface of a semiconductor substrate when a voltage is applied to an assist gate. Accordingly, as it is not necessary to form an impurity region for forming a bit line in a memory cell area, the non-volatile semiconductor memory device can be reduced in size. Such a technique is described, for example, in Y. Sasago, et. al., “90-nm-node multi-level AG-AND type flash memory with cell size of true 2 F2/bit and programming throughput of 10 MB/s,” IEDM Tech. Dig., (2003) p. 823.
The AG-AND type flash memory has a semiconductor substrate and an insulating film formed on the semiconductor substrate, and includes a memory cell area and a peripheral circuit area adjacent to the memory cell area. The memory cell area includes a floating gate and a control gate arranged on an upper surface of the floating gate, and a plurality of memory cells are formed in the memory cell area.
The peripheral circuit area includes a plurality of assist gates formed on the insulating film and an electrode portion applying a voltage to a lower surface of the assist gate.
In the conventional AG-AND type flash memory structured as above, at the time of writing, a voltage is applied to one assist gate to form an inversion layer under the assist gate, to which a voltage is applied. Then, a voltage is applied to the other assist gate to form an inversion layer under this assist gate, to which a voltage is applied. Accordingly, a write current is generated under the floating gate, so that data is written in the floating gate arranged between two assist gates. A reading operation and an erasing operation are performed also by applying voltages of various magnitudes to the assist gates.
During the reading operation or the like, voltages applied to respective assist gates and the inversion layer are different in magnitude. Therefore, depending on each operation and position, magnitude of the voltage applied to the insulating film formed under the assist gate or the like is considerably different. Meanwhile, the insulating film formed on the semiconductor substrate has a uniform thickness.
An example of a non-volatile semiconductor memory device having a gate insulating film different in thickness from a position to a position formed on a semiconductor substrate is described in Japanese Patent Laying-Open No. 2001-044395. The non-volatile semiconductor memory device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a memory cell transistor formed on the gate insulating film within the memory cell, and a select transistor. The gate insulating film of the select transistor has a thickness larger than that of a tunneling insulating film of the memory cell transistor. According to this non-volatile semiconductor memory device, an operation speed of the select transistor can be improved.
In addition, an example of a non-volatile semiconductor memory device having a gate insulating film different in thickness from a position to a position formed on a semiconductor substrate is described in Japanese Patent Laying-Open No. 2000-269361.
The non-volatile semiconductor memory device has a memory cell including a memory cell transistor and a select transistor. The memory cell transistor and the select transistor are different from each other in a film thickness and a threshold voltage.
In the conventional AG-AND type flash memory, a high voltage is applied to a part of the insulating film during various operations, with the result that reliability has not been ensured. In particular during the writing operation, as a voltage larger than in other type of operation is applied to each assist gate, a large voltage is applied to a part of the insulating film formed under the assist gate, which results in difficulty in achieving ensured reliability.
If a thickness of the insulating film is set using a position to which a high voltage is applied as a reference, a writing speed is disadvantageously lowered.
In addition, none of the inventions according to Japanese Patent Laying-Open Nos. 2001-044395 and 2000-269361 is directed to ensuring reliability of the insulating film, nor related to an AG-AND type flash memory.